Moinuddin K. Qureshi

Associate Professor
Computer Systems and Software (TIG within ECE)
School of Electrical and Computer Engineering


Research Interests: Computer Architecture, Memory Systems, and Architecting Emerging Technologies


Email: moin at ece dot gatech dot edu
Office: KACB 2312, 266 Ferst Drive, Atlanta GA30318

MICRO 2015 

I am honored to be serving as the Program Chair for MICRO 2015.  With the aim of improving the quality of the review process, MICRO 2015 will employ a model in which the authors (of papers likely to be discussed at the PC meeting) will get an option to revise their papers during the rebuttal period to address the concerns and incorporate the suggestions of the reviewers.  The author response period  has been extended to three weeks.  More details on the new review model can be found here If you have any suggestions or feedback about the new process, or in general about improving the quality of the review process of our conferences, please feel free to email me.


Teaching
 
Advanced Topics in Memory Systems [ECE8873, now ECE7103A]:   Spring 2015, Spring 2014, Spring 2013, Spring 2012
Advanced Computer Architecture [ECE4100/ECE6100]: Spring 2015, Spring 2014, Fall 2012
Architecture, Concurrency, and Energy [ECE3065]: Spring 2014, Fall 2013

Book: Phase Change Memory: From Devices to Systems (Synthesis Lectures on Computer Architecture)
by Moinuddin K. Qureshi, Sudhanva Gurumurthi and Bipin Rajendran, Morgan Claypool Publishers Dec 2011



PhD Students and Research Topics

1. Chia-Chen Chou:  Architecting Heterogeneous Memory Systems, 3D Memory, Bandwidth-Efficient Memories
2. Prashant Nair:  Low-Latency Memory Systems, and Addressing Memory Reliability, Variability, and Scalability
3. Jian Huang (co-advised with Karsten Schwan): NVRAM Aware Storage Systems
4. Vinson Young:  Secure Non-Volatile Memories
5. Swamit Tannu:  Algorithms and Architectures for Hierarchical Temporal Memories, Neuromorphic Computing


Publications  (Link to Google Scholar page)


2015
  • BATMAN: Maximizing Bandwidth Utilization for Hybrid Memory Systems (pdf)
    Chia-Chen Chou, Aamer Jaleel,  Moinuddin K. Qureshi
    Technical Report, TR-CARET-2015-01 (March 9, 2015)


  • BEAR: Techniques for Mitigating  Bandwidth Bloat in Gigascale DRAM Caches
    Chia-Chen Chou, Aamer Jaleel,  Moinuddin K. Qureshi
    To appear in the
    International Symposium on Computer Architecture (ISCA), 2015


  • Unified Address Translation for Memory-Mapped SSDs
  • Jian Huang, Anirudh Badam, Moinuddin K. Qureshi, Karsten Schwan
    To appear in the
    International Symposium on Computer Architecture (ISCA), 2015

  • AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems
    Moinuddin K. Qureshi,
    Dae Hyun Kim, Samira Khan, Prashant Nair, Onur Mutlu
    To appear in the
    International Conference on Dependable Systems and Networks (DSN), 2015


  • Reducing Refresh Power in Mobile Devices with Morphable ECC
    Chia-Chen Chou, Prashant Nair, Moinuddin K. Qureshi
    To appear in the
    International Conference on Dependable Systems and Networks (DSN), 2015 
  • NVRAM-Aware Logging in Transactional Systems (pdf)
    Jian Huang, Karsten Schwan,  Moinuddin K. Qureshi
    Appears in the
    International Conference on Very Large Data Bases (VLDB), 2015 
  • DEUCE: Write-Efficient Encryption for Secure Non-Volatile Memories (pdf)
    Vinson Young, Prashant Nair,  Moinuddin K. Qureshi
    Appears in the
    International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS), 2015  
  • Reducing Read Latency of Phase Change Memories via Early Read and Turbo Read  (pdf)
    Prashant Nair, Chia-Chen Chou, Bipin Rajendran,  and Moinuddin K. Qureshi
    Appears in the International Symposium on High Performance Computer Architecture (HPCA), 2015 


2014
  • Balancing Context Switch Penalty and Response Time with Elastic Time Slicing (pdf)
    Nagakishore Jammula, Moinuddin K. Qureshi, Ada Gavrilovska, and Jongman Kim
    Appears in the International Conference on High Performance Computing (HiPC), 2014  (Best Paper Award) 
  • CAMEO:  A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache (pdf)
    Chia-Chen Chou, Aamer Jaleel,  and Moinuddin K. Qureshi
    Appears in the International Symposium on Microarchitecture (MICRO), 2014 
  • Citadel:  Efficiently Protecting Stacked Memoreis Against Large Granularity Failures (pdf)
    Prashant Nair, David Roberts, and Moinuddin K. Qureshi
    Appears in the International Symposium on Microarchitecture (MICRO), 2014  
  • Architectural Support for Mitigating Row Hammering in DRAM Memories (pdf)
    Daehyun Kim, Prashant Nair, and Moinuddin K. Qureshi
    Appears in Computer Architecture Letters (CAL), May 2014


2013
  • ArchShield: Architectural Framework for Assisting DRAM Scaling by Tolerating High Error Rates (pdf)
    Prashant Nair, Daehyun Kim, and Moinuddin K. Qureshi
    Appears in the International Symposium on Computer Architecture  (ISCA) 2013
  • Operating SECDED Based Caches at Ultra-Low Voltage with FLAIR (pdf)
    Moinuddin K. Qureshi and Zeshan Chishti
    Appears in the International Conference on Dependable Systems and Network (DSN) 2013
  • A Case for Refresh Pausing in DRAM Memory Systems (pdf)
    Prashant Nair, Chia-Chen Chou, and Moinuddin K. Qureshi
    Appears in the International Symposium on High Performance Computer Architecture  (HPCA) 2013

2012
  • Fundamental Latency Trade-offs in Architecting DRAM Caches  (pdf, slides)
    Moinuddin K. Qureshi and Gabriel Loh
    Appears in the International Symposium on Microarchitecture  (MICRO) 2012

  • FLEXclusion:  Balancing Capacity and On-Chip Traffic via Flexible Exclusion  (pdf)
    J. Sim,  J. Lee, Moinuddin K. Qureshi, and Hyesoon Kim
    Appears in the International Symposium on Computer Architecture (ISCA) 2012

  • PreSET: Improving Read Write Performance of Phase Change Memories by Exploiting Asymmetry in Write Times (pdf, slides)
    Moinuddin K. Qureshi, Michele Franceschini, Luis Lastras and Ashish Jagmohan
    Appears in the International Symposium on Computer Architecture (ISCA) 2012


2011
  • Pay-As-You-Go:  Low Overhead Hard-Error Correction for Phase Change Memories (pdf, slides)
    Moinuddin K. Qureshi
    Appears in the International Symposium on Microarchitecture (MICRO) 2011
  • Practical and Secure PCM Systems by Online Detection of Malicious Write Streams  (pdf, slides)
    Moinuddin K. Qureshi, Andre Seznec, Luis Lastras, Michele Franceschini 
    Appears in the International Conference on High Performance Computer Architecture (HPCA) 2011

2010

  • Feedback Driven Pipelined Parallelism.
    M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, and Yale N. Patt
    Appears in the International Conference on Parallel Architecture and Compilation Technique (PACT) 2010.

  • Morphable Memory System: A Robust Architecture for Exploiting Multi-Level Phase Change Memories.
    Moinuddin K. Qureshi, Michele Franceschini, Luis Lastras, and John Karidis
    Appears in the International Symposium on Computer Architecture (ISCA) 2010.

  • Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures.
    M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt
    Appears in the IEEE MICRO Special Issue on Top Picks from Microarchitecture Conferences (IEEE MICRO 2010).

  • Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing.
    Moinuddin K. Qureshi, Michele Franceschini and Luis Lastras
    Appears in the International Symposium on High Performance Computer Architecture (HPCA) 2010.

2009
  • Enhancing Lifetime and Security of Phase Change Memories via Start-Gap Wear Leveling.
    Moinuddin K. Qureshi, John Karidis, Michele Franceschini, Viji Srinivasan, Luis Lastras and Bulent Abali
    Appears in the International Symposium on Microarchitecture (MICRO) 2009.

  • A Tagless Coherence Directory.
    Jason Zebchuk, Viji Srinivasan, Moinuddin K. Qureshi, and Andreas Moshovos
    Appears in the International Symposium on Microarchitecture (MICRO) 2009.

  • Scalable High-Performance Main Memory System Using Phase-Change Memory Technology.
    Moinuddin K. Qureshi, Viji Srinivasan, and Jude A. Rivers
    Appears in the International Symposium on Computer Architecture (ISCA) 2009.

  • Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures.
    M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt
    Appears in the International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS) 2009.
  • (One of the 13 computer architecture papers of 2009 selected as Top Picks by IEEE Micro)

  • Adaptive Spill-Receive for Robust High-Performance Caching in CMPs.
    Moinuddin K. Qureshi
    Appears in the International Conference on High Performance Computer Architecture (HPCA) 2009.

2008
  • Adaptive Insertion Policies for Managing Shared Caches.
    Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon Stelly Jr. and Joel Emer
    Appears in the International Conference on Parallel Architectures and Compiler Techniques (PACT) 2008.

  • Feedback Driven Threading: Power-Efficient and High-Performance Execution of Multithreaded Workloads on CMPs.
    M. Aater Suleman, Moinuddin K. Qureshi, and Yale N. Patt.
    Appears in the International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS) 2008.

  • Set-Dueling Controlled Adapative Insertion for High-Performance Caching.
    Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt,  Simon C. Steely Jr., and Joel Emer.
    Appears in the IEEE MICRO Special Issue on Top Picks from Microarchitecture Conferences (IEEE MICRO 2008).

2007
  • Adaptive Insertion Policies for High-Performance Caching.
    Moinuddin K.Qureshi, Aamer Jaleel, Yale N. Patt,  Simon C. Steely Jr., and Joel Emer.
    Appears in the International Symposium on Computer Architecture (ISCA) 2007
  • (One of the 10 computer architecture papers of 2007 selected as Top Picks by IEEE Micro)

  • Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines.
    Moinuddin K. Qureshi, M. Aater Suleman, and Yale N. Patt.
    Appears in the International Symposium on High-Performance Computer Architecture (HPCA) 2007.

2006

2005


Bio:  Dr. Moinuddin Qureshi joined the faculty of the Georgia Institute of Technology as an Associate Professor in 2011. His research interests include computer architecture, scalable memory systems, fault tolerant computing, and analytical modeling of computer systems. He worked as a research staff member at IBM T.J. Watson Research Center from 2007 to 2011. While at IBM, he contributed to the design of efficient caching algorithms for Power 7 processors. He was awarded the IBM outstanding technical achievement award for his studies on emerging memory technologies for server processors. He holds more than a dozen U.S. patents and has more than two-dozen publications in flagship architecture conferences. He received the Intel Early Faculty Career award and the NetApp Faculty Fellowship in 2012.  He has served as a Program Committee member for several architecture conferences, including ISCA (2009, 2010, 2011, 2012), MICRO (2010, 2011), and HPCA (2015). He received his Ph.D. (2007) and M.S. (2003), both in Electrical Engineering from the University of Texas at Austin, and Bachelor of Electronics Engineering (2000) degree from University of Mumbai.